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1 2.5mhz integrated power management ic with i 2 c compatible interface ISL80083 ISL80083 is an integrated mini power management ic (mini-pmic) for powering low-voltage microprocessor, or applications using a single li-ion or li-polymer cell battery to power multiple voltage rails. ISL80083 integrates a high-efficiency 2.5mhz synchronous step-down converter, a low-input low-dropout linear regulator, 33mhz oscillator, level shift, and input supply select. the 2.5mhz pwm switching frequency allows for the use of very small external inductors and capacitors. the step-down converter can enter skip mode under light load conditions to further improve the efficiency and maximize the battery life. for noise sensitive applications, it can also be programmed through i 2 c interface to operate in forced pwm mode, regardless of the load current condition. the i 2 c interface supports on-the-fly control of the output voltage from 0.625v to 2.225v at 25mv/step size for dynamic power saving. the step-down converter can supply up to 800ma load current. ISL80083 also provides a 300ma low dropout (ldo) regulator. the input voltage range is from 2.6v to 5.5v allowing it to be powered from one of the on-chip st ep-down converters or directly from the battery. the default ldo output comes with factory pre-set fixed output voltage op tions between 0.9v to 3.6v. ISL80083 is available in a 2.11mm x 2.13mm 25 ball csp package. features ? 800ma synchronous step-down converter and 300ma, general-purpose ldo ? 400kb/s i 2 c-bus series interface transfers the control data between the host controller and the ISL80083 ? fixed smps output voltage i 2 c programmability - at 25mv/step. . . . . . . . . . . . . . . . . . . . . . 0.625v to 2.225v ?ldo output voltage i 2 c programmability - at 50mv/step. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9v to 3.6v ? 33mhz oscillator ? level shift from 1.8v to 3v with enable ?input select ?switcher i 2 c programmable skip mode under light load or forced fixed switching frequency pwm mode applications ?power cable figure 1. efficiency vs load (3.3v in , t a = +25c) 40 50 60 70 80 90 100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output load (a) efficiency (%) 1v - pfm caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. may 15, 2013 fn7886.1
ISL80083 2 fn7886.1 may 15, 2013 pin configuration ISL80083 (25 ball csp 2.11 x 2.13mm) top view vin_host vselect clk2p3out phase clk2p3in reset voldo gndldo sclk vin_remote osc_en v3clamp gnd uart_en cfg2 1vaux pgnd cfg2_cr lsrx_cr fb -oscout sdat lsrx +oscout oscgnd a b c d e 1 234 5 pin descriptions pin number pin name description a1 -oscout negative terminal of the precisio n 33mhz oscillator differential output. a2 +oscout positive terminal of the precision 33mhz oscillator differential output. a3 oscgnd isolated ground for the internal 33mhz oscillator. a4 clk2p3in 2.3v input for the 33mhz oscillator. connect a 220nf capacitor from clk2p3out to oscgnd. a5 clk2p3out 2.3v internal ldo output for the 33mhz oscillator. connect clk2p3in to clk2p3out along with a 220nf capacitor for low noise performance. b1 cfg2 this is the output of the level shifter from the cfg2_cr rail control signal shifting from 1.8v to 3v. b2 lsrx this is the output of the level shifter from the lsrx_cr rail control signal shifting from 1.8v to 3v. b3 uart_en level shift of lsrx logic enable control. the output ls rx is in high z state when uart _en is pulled low. there is a 125k pull-down resistor from this pin to gnd. b4 reset this is a totem pole output to indicate a fault mode. the output is low if any of the fault is detected. the output is high during normal operation. b5 v3clamp this rail is a 3v ldo sourcing from vselect. c1 cfg2_cr this is the input to the level shifter for the co nfig2 rail control signal shifting from 3v to 1.8v. c2 lsrx_cr this is the input to the level sh ifter from the lsrx rail control signal. c3 voldo output of the ldo.
ISL80083 3 fn7886.1 may 15, 2013 c4 gndldo power ground for ldo. c5 gnd system ground for analog and digital circuitry. d1 vin_remote input voltage secondar y for cases where vin_host is valid, vin_remote is held off ic. if there is 2.6v present and vin host is not valid, then the pass mosfet turns on. if this volt age is greater than 4.5v, then its pass mosfet turn off. d2 osc_en oscillator control pin. connect to logic high will allow all outputs to operat e normally and smps in pwm. connecting to logic low will disable the 33mhz oscillator, 1vaux, and allo w the smps to operate in high light load efficiency pfm. there is a 125k pull-up resistor from this pin to 1.8v. d3 sclk i 2 c interface clock pin. d4 sdat i 2 c interface data pin. d5 1vaux this rail is a low impedance pass pfet switch sourcing from switcher?s output thru the vfb pin. e1 vin_host input voltage primary for the ic. if there is 2.6v pres ent, then the pass mosfet turns on. if this voltage is greater than 4.5v, then its pass mosfet turn off. e2 vselect input voltage for buck converter switcher, v3clamp, ldo, and it also serves as the po wer supply pin for the whole inte rnal digital/analog circuits. e3 phase switching node for dc to dc converter; connect to one terminal of the inductor. e4 pgnd power ground for switcher. e5 fb feedback pin for switcher; connect external voltage divide r resistors between switcher output, this pin and ground. for fixed output versions, connect this pin directly to the switcher output. pin descriptions (continued) pin number pin name description ordering information part number (notes 1, 2, 3) part marking fb (v) slv ldo (v) temp. range (c) package tape & reel (pb-free) pkg. dwg. # ISL80083iiz-t 80083 adj 3.3 -40 to +85 25 ball wlcsp w5x5.25b ISL80083iiz-tk 80083 adj 3.3 -40 to +85 25 ball wlcsp w5x5.25b ISL80083iiz-ts 80083 adj 3.3 -40 to +85 25 ball wlcsp w5x5.25b notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free wlcsp and bga packaged products employ special pb-free material sets; molding compounds/die attach mat erials and snagcu - e1 solder ball terminals, which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free wlcsp and bga packaged products are msl classified at pb-free pe ak reflow temperatures that meet or exceed the pb-free requirem ents of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL80083 . for more information on msl please see tech brief tb363 .
ISL80083 4 fn7886.1 may 15, 2013 block diagram selector logic 2.5v to 4.5v pass range prefer ?host? input vselect ldo buck control i 2 c sstime buck vout ldo vout pwm/pfm osc ldo osc 33mhz 1v aux 3v clamp out level shift 3v to 1.8v (lsrx hi-z out disable) agnd -oscout oscgnd agnd sclk sdat cfg2 lsrx_cr clk2p3out 1v aux 500ma fb pgnd phase voldo v3clamp 15ma host remote 1.8v 1.0v cfg2_cr vin remote vin host uart_en lsrx 10f 1f 10f 1f 10f 1h q1 q2 q3 q4 q5 q6 q7 +oscout clk2p3in oscgnd 220nf c1 c2 c3 l1 c4 c5 c6 ldo gnd ldognd fault vin uv ovp/ uvp ocp otp ldo ov ldo uv v3clamp 5k 5k osc_en control reset 125k 125k 1.8v table 1. typical application part list parts description manufacturer part number specifications size l1 inductor tdk vsf302512t-1r0 1.0h/1.8a/33m ? 3.0mmx2.5mmx1.2mm c1, c4, c5 input and output capacitor murata grm21br60j106ke19l 10f/6.3v 0402 c2, c3 output capacitor murata grm185r60j105ke26d 1f/6.3v 0201 c6 bias capacitor various grm185r60j224ke26d 220nf/6.3v 0201
ISL80083 5 fn7886.1 may 15, 2013 absolute maximum ratings (refer to ground) thermal information vin_host, vin_remote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3v (dc) to 22v (dc) vselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3v (dc) to 6.5v (dc) or 7v (20ms) phase . . . . . . . . . . . . . . . . . . . . .-1.5v (100ns)/-0.3v (dc) to 6.5v (dc) or 7v (20ms) v3pclamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v agnd, oscgnd, pgnd, gndldo . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v 1vaux, cfg2, cfg2_cr, lsrx, lsrx_cr . . . . . . . . . . . . . . . -0.3v to 3.6v reset , sdat, sclk, uart_en, voldo . . . . . . . . . . . . . . . . . . -0.3v to 3.6v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.9v esd ratings human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c101d) . . . . . . . . . . . . . 1kv latch up (tested per jesd78b, class ii, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) csp package (notes 4, 5) . . . . . . . . . . . . . . 70 0.9 maximum junction temperature range . . . . . . . . . . . . . .-40c to +150c recommended junction temperature range . . . . . . . . . . 0c to +125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-40c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions vin_host, vin_remote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 20v smps output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 800ma ldo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0ma to 300ma operating ambient temperature . . . . . . . . . . . . . . . . . . . . . . 0c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for jc , the ?case temp? location is taken at the package top center. electrical specifications unless otherwise noted, all parameter limits are guaran teed over the recommended operating conditions and the typical specifications are measured at the following conditions: t a = +25c, vin_host or vin_remote = 3.3v. for ldo, vselect = voldo + 0.5v to 5.5v, l1 = 1.0h, c1 = c4 = c5 = 10f, c2 = c3 = c6 = 1f, i out = 0a for smps and ldo (see figure 1 for more details). boldface limits apply across the operating temperature range, -40c to +85c. parameter symbol test conditions min (note 6) typ max (note 6) unit vin_host or vin_remote voltage range 2.7 20 v vselect undervoltage lockout threshold v uvlo rising, i out = 0a for both smps and ldo 2.40 2.56 2.62 v falling 2.30 2.46 2.57 v quiescent supply current on vselect i vselect all outputs no loading 150 500 a thermal shutdown 155 c thermal shutdown hysteresis 30 c input selector vin_host p-channel mosfet on-resistance q1 vselect = 3.3v, i o = 200ma 0.20 ? vin_remote p-channel mosfet on- resistance q2 vselect = 3.3v, i o = 200ma 0.20 ? minimum pass range voltage v in_min 2.2 2.7 v maximum pass range voltage v in_max 4.5 5.52 v smps output start up voltage vselect = 3.3v, pwm 0.950 1.000 1.050 v line regulation vselect = v o + 0.5v to 5.5v (minimal 2.5v) 0.1 %/v p-channel mosfet on-resis tance q5 vselect = 3.3v, i o = 200ma 0.14 0.18 ? n-channel mosfet on-resistance q6 vselect = 3.3v, i o = 200ma 0.05 0.08 ? p-channel mosfet peak current limit i pk 1 1.4 1.7 a pwm switching frequency f s f osc /13 2.5 mhz sw minimum on-time v fb = 2v 70 ns
ISL80083 6 fn7886.1 may 15, 2013 ss time vout rise time 1 ms soft-discharge resistor resistor from phase to pgnd 115 ? 1vaux p-channel mosfet on-resistance q7 i o = 200ma 0.07 ? shutdown delay time sleep mode from osc_en < 0.45v 1.5 ms ldos internal peak current limit 200 425 540 ma voldo output start-up voltage vselect = 3.3v 1.71 1.80 1.89 v v3clamp output voltage i 3p3v = 15ma, vselect = 3.3v 2.7 3.0 3.3 v voldo power supply rejection ratio i o = 300ma @ 1khz, vselect = 3.3v, v o = 2.6v, t a = +25c 55 db voldo output voltage noise vselect = 3.3v, i o = 10ma, t a = +25c, bw = 10hz to 100khz 45 v rms level shft cfg2_cr logic high input 1.4 v cfg2_cr logic low input 0.4 v lsrx_cr logic high input uart_en > 1.2v 1.4 v lsrx_cr logic low input uart_en > 1.2v 0.4 v cfg2 logic high output cfg2_cr > 1.2v, 3.3k pull-down 2.8 3.3 v cfg2 logic low output cfg2_cr < 0.4v, 3.3k pull-down 0.4 v lsrx logic high output uart_en > 1.2v, lsrx_cr > 1.2v, 1m pull-down 2.4 3.2 v lsrx logic low output uart_en > 1.2v, lsrx_cr < 0.4v, 1mk pull-down 0.4 v cfg2 low-to-high prop delay cfg2_cr > 1.2v 50 ns cfg2 high-to-low prop delay cfg2_cr < 0.4v 50 ns lsrx low-to-high prop delay uart_en > 1.2v, lsrx_cr > 1.2v 50 ns lsrx high-to-low prop delay uart_en > 1.2v, lsrx_cr < 0.4v 50 ns lsrx output impedance high z uart_en < 0.6v 10 m ? oscillator clk2p3out voltage i 2p2v = 15ma, vselect = 2.8v to 5.5v 2.25 2.30 2.35 v output voltage v oh single-ended (+oscout or -oscout) 700 mv output voltage v ol single-ended (+oscout or -oscout) 100 mv frequency measured from +oscout to -oscout, vselect = 3.3v 33.00 mhz jitter measured from +oscout to -oscout, vselect = 3.3v 6 ps rms/ cycle clk_osc disable time - sleep mode delay from osc_en < 0.45v 1 ms clk_osc start time from sl eep from clk_en > 1.2v 100 s electrical specifications unless otherwise noted, all parameter limits are guaran teed over the recommended operating conditions and the typical specifications are measured at the following conditions: t a = +25c, vin_host or vin_remote = 3.3v. for ldo, vselect = voldo + 0.5v to 5.5v, l1 = 1.0h, c1 = c4 = c5 = 10f, c2 = c3 = c6 = 1f, i out = 0a for smps and ldo (see figure 1 for more details). boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) unit
ISL80083 7 fn7886.1 may 15, 2013 i 2 c interface timing specifications for scl and sda pins, unless otherwise noted. symbol parameter test conditions min (note 6) typ max (note 6) units c pin pin capacitance 15 pf f scl scl frequency 400 khz t sp pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing v il , until sda exits the v il to v ih window 900 ns t buf time the bus must be free before the start of a new transmission sda crossing v ih during a stop condition, to sda crossing v ih during the following start condition 1300 ns t low clock low time measured at the v il crossings 1300 ns t high clock high time measured at the v ih crossings 600 ns t su:sta start condition set-up time scl rising edge to sda falling edge; both crossing v ih 600 ns t hd:sta start condition hold time from sda falling edge crossing v il to scl falling edge crossing v ih 600 ns t su:dat input data set-up time from sda exiting the v il to v ih window, to scl rising edge crossing v il 100 ns t hd:dat input data hold time from sc l rising edge crossing v ih to sda entering the v il to v ih window 0 ns t su:sto stop condition set-up time from scl rising edge crossing v ih , to sda rising edge crossing v il 600 ns t hd:sto stop condition hold time for read, or volatile only write from sda rising edge to scl falling edge; both crossing v ih 1300 ns t dh output data hold time from scl falling edge crossing v il , until sda enters the v il to v ih window 0 ns t r sda and scl rise time from v il to v ih 20 + 0.1 x cb 250 ns t f sda and scl fall time from v ih to v il 20 + 0.1 x cb 250 ns cb capacitive loading of sda or scl total on-chip and off-chip 10 400 pf rpu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f for cb = 400pf, max is about 2k ~2.5k for cb = 40pf, max is about 15k ~20k 1 k note: 6. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established by characterization and are not production tested.
ISL80083 8 fn7886.1 may 15, 2013 typical performance curves and waveforms figure 2. efficiency vs load (3.3v in , t a = +25c) figure 3. power dissipation vs load (3.3v in , t a = +25c) figure 4. vout regulation vs load (3.3v in , t a = +25c) figure 5. vout regulation vs load (3.3v in , t a = +25c) figure 6. start-up with vin ho st = 3.3v at no load (pfm) figure 7. start-up with vin ho st = 3.3v at no load (pwm) 40 50 60 70 80 90 100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output load (a) efficiency (%) 1v - pfm 1v - pwm 0 50 100 150 200 250 300 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output load (a) power dissipation (mw) 1v - pfm 1v - pwm 0.970 0.980 0.990 1.000 1.010 1.020 1.030 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output load (a) output voltage (v) 1v - pwm 1v - pfm 1.785 1.790 1.795 1.800 1.805 1.810 1.815 0 30 60 90 120 150 180 210 240 270 300 output load (a) output voltage (v) 1.8v ldo vin host 5v/div smps 1v/div vin remote 1v/div vldo 2v/div reset b 2v/div 1ms/div vin host 5v/div smps 1v/div vin remote 1v/div vldo 2v/div reset b 2v/div 1ms/div .
ISL80083 9 fn7886.1 may 15, 2013 figure 8. shut down vin host = 3.3v at no load (pfm) figure 9. shut down vin host = 3.3v at no load (pwm) figure 10. start-up vin host = 3.3v at 0.8a load (pwm) figure 11. shutdown vin host = 3.3v at 0.8a load (pwm) figure 12. start-up vin host = 3.3v at 0.8a load (pfm) f igure 13. shutdown vin host = 3.3v at 0.8a load (pfm) typical performance curves and waveforms (continued) vin host 5v/div smps 1v/div vin remote 1v/div vldo 2v/div reset b 2v/div 10ms/div vin host 5v/div smps 1v/div vin remote 1v/div vldo 2v/div reset b 2v/div 10ms/div vin host 5v/div smps 1v/div vin remote 1v/div vldo 2v/div reset b 2v/div 1ms/div vin host 5v/div smps 1v/div vin remote 1v/div vldo 2v/div reset b 2v/div 10ms/div vin host 5v/div smps 1v/div vin remote 1v/div vldo 2v/div reset b 2v/div 1ms/div vin host 5v/div smps 1v/div vin remote 1v/div vldo 2v/div reset b 2v/div 10ms/div
ISL80083 10 fn7886.1 may 15, 2013 figure 14. start-up vin remote = 3.3v at no load (pwm) figure 15. shutdown vin remote = 3.3v at no load (pwm) figure 16. start-up vin remote = 3.3v at no load (pfm) f igure 17. shutdown vin remote = 3.3v at no load (pfm) figure 18. start-up vin remote = 3.3v at 0.8a load (pfm) figure 19. shutdown vin remote = 3.3v at 0.8a load (pfm) typical performance curves and waveforms (continued) vin host 1v/div smps 1v/div vin remote 5v/div vldo 2v/div reset b 2v/div 1ms/div vin host 1v/div smps 1v/div vin remote 5v/div vldo 2v/div reset b 2v/div 10ms/div vin host 1v/div smps 1v/div vin remote 5v/div vldo 2v/div reset b 2v/div 1ms/div vin host 1v/div smps 1v/div vin remote 5v/div vldo 2v/div reset b 2v/div 10ms/div vin host 1v/div smps 1v/div vin remote 5v/div vldo 2v/div reset b 2v/div 1ms/div vin host 1v/div smps 1v/div vin remote 5v/div vldo 2v/div m4 reset b 2v/div reset b 2v/div vldo 2v/div 10ms/div
ISL80083 11 fn7886.1 may 15, 2013 figure 20. start-up vin remote = 3.3v at 0.8a load (pwm) figure 21. shutdown vin remote = 3.3v at 0.8a load (pwm) figure 22. jitter at no load (pwm), vin = 3.3v figure 23. jitter at full load (pwm), vin = 3.3v figure 24. steady state at no load (pwm), vin = 3.3v figure 25. steady state at no load (pfm), vin = 3.3v typical performance curves and waveforms (continued) vin host 1v/div smps 1v/div vin remote 5v/div vldo 2v/div reset b 2v/div 1ms/div vin host 1v/div smps 1v/div vin remote 5v/div vldo 2v/div reset b 2v/div 10ms/div lx 1v/div 5ns/div lx 1v/div 5ns/div lx 2v/div smps 10mv/div il 0.5a/div 200ns/div lx 2v/div smps 20mv/div il 0.5a/div 50ms/div
ISL80083 12 fn7886.1 may 15, 2013 figure 26. steady state at 0.8a load (pwm), vin = 3.3v figure 27. steady state at 0.8a load (pfm), vin = 3.3v figure 28. load transient (pwm ), vin = 3.3v figure 29. load transient (pfm), vin = 3.3v figure 30. output short circuit, vin = 3.3v figure 31. overcurrent protection, vin = 3.3v typical performance curves and waveforms (continued) lx 2v/div smps 10mv/div il 0.5a/div 200ns/div lx 5v/div smps 10mv/div il 0.5a/div 200ns/div smps ripple 50mv/div iout 0.5a/div 50s/div il 0.5a/div smps ripple 100mv/div 50s/div lx 2v/div smps 1v/div il 2a/div reset b 2v/div 5s/div smps 0.5v/div il 1a/div reset b 2v/div 10ms/div
ISL80083 13 fn7886.1 may 15, 2013 figure 32. pfm to pwm transition, vin = 3.3v figure 33. pwm to pfm transition, vin = 3.3v figure 34. overvoltage protection, vin = 3.3v figu re 35. over-temperature protection, vin = 3.3v typical performance curves and waveforms (continued) lx 2v/div smps ripple 20mv/div il 0.5a/div 200ma mode transition, completely enter to pwm at 206ma 5s/div lx 2v/div smps ripple 20mv/div il 0.5a/div back to pfm at 110ma 5s/div lx 2v/div smps 2v/div il 1a/div reset b 2v/div 200s/div smps 0.5v/div reset b 1v/div 1ms/div t a = +150c
ISL80083 14 fn7886.1 may 15, 2013 input selector operation input power for the ISL80083 is au tomatically selected from one of two source pins; vin_host or vin_remote. the rising slew rate of vin_host or vin_remote is assumed to be 120v/ms or less. the selector output is vs elect and should be de-coupled with a 10f or greater mlcc. in addition to choosing which input will provide power, the selector provides de-bounce, a soft-start to limit inrush current and it protec ts other circuit blocks of the ISL80083 against overvoltage. typically, when either input pin exceeds 2.2v, it is considered ?in range? and its switch is acti vated over approximately 300s, which limits the surge to the vselect capacitor. once complete, the selector provides typically a 200m path between the selected input and vselect. the un-selected input is isolated from vselect and <5a will flow in or out of the input. in the case that both inputs enter the selectable range at the same moment, the vin_host will be selected. otherwise, the selector will simply choose the first input that comes in range. typically, overvoltage is considered to be greater than 4.5v. if this condition occurs, the selector will disconnect this input within 5s. in the case that neither input is considered in range, the selector will isolate both inputs from vselect and the ISL80083 will remain in an un-powered state until an input comes in range. smps introduction the smps converter on isl8008 3 uses the peak-current-mode pulse-width modulation (pwm) cont rol scheme for fast transient response and pulse-by-pulse current limiting. the converter is able to supply up to 800ma load current. the default output voltage is 1v upon start-up and can be programmed via the i 2 c interface in the range of 0.625v to 2.225v at 25mv/step with a programmable slew rate using the register smps_out. when osc_en is pulled low, the i 2 c register 03h switches over. the default output is still 1v and will operate in pfm. optionally, the smps can be programmed to be actively discharged via an on-chip bleeding resistor (typical 115 ? ) when the converter is disabled. soft-start upon vselect engaged, the output is defaulted to 1v with a rise time of about 1ms to reduce the in-rush. then 1ms of delay later, the ldo will rise to 1.8v in 20ms. see figure 36, start-up sequence for more details. reset reset is the totem pole window comparator output that continuously monitors the buck regulator output voltage via the fb pin. reset is actively held low when disabled and during the buck regulator soft-start period. reset goes high after 1ms or 8.4ms delay as long as the output voltages of the switcher and ldo are above 95% of the nominal regulation voltage. the delay time is controlled via the i 2 c interface. the default delay time is 1ms. when v out drops 10% below the nominal regulation voltage, the ISL80083 pulls reset low. any fault condition forces reset low until the fault condition is cleared by attempts to soft- start. overcurrent protection the overcurrent protection is real ized by monitoring the current through the pfet, q5 in the block diagram. upon detection of overcurrent condition, the upper mosfet will be immediately turned off and will not be turned on again until the next switching cycle. upon detection of the in itial overcurrent condition, the overcurrent fault counter is set to 1. if, on the subsequent cycle, another overcurrent condition is detected, the oc fault counter will be incremented. if there are 17 sequential oc fault detections, the regulator will be shut down under an overcurrent fault condition. an overcurrent fa ult condition will result in the switcher and ldo attempting to restart in a hiccup mode within the delay of 600s. at the end of the wait peri od, the fault counters are reset and soft-start is attempted again. likewise, an overcurrent on the ldo output still results in the switcher and ldo attempting to restart in a hiccup mode within the delay of 600s. the 1v smps and 1vaux will soft-start first, then the ldo will attempt to start 1ms later. the ldo output may not reach regulation unless an ov ercurrent condition is removed. once an overcurrent fault is removed, reset will transition high after the delay time when the ldo voltage reaches regulation. negative current protection similar to the overcurrent, the negative current protection is realized by monitoring the current across the lowside n-fet, as shown in the ?block diagram? on page 4. when the valley point of the inductor current reaches -1a for 2 consecutive cycles, both p-fet and n-fet are off. the 115 parallel to the n-fet will activate discharging the output in to regulation. the control will begin to switch when output is wi thin regulation. the regulator will be in pfm for 20s before switching to pwm if necessary. undervoltage lockout (uvlo) an undervoltage lockout (uvlo) circuit is provided on the ISL80083. the uvlo circuit block can prevent abnormal operation in the event that the supply voltage is too low to guarantee proper operation. the uvlo on vselect is set for a typical 2.49v with 100mv hysteresis. when the input voltage is sensed to be lower than the uvlo threshold, all the related channels are disabled. low dropout operation the smps converter features low dropout operation, which maximizes the battery life. when the input voltage drops to a level that the converter can no longer operate under switching regulation to maintain the output voltage, the p-channel mosfet is completely turned on (100% duty cycle). the dropout voltage under such conditions is the product of the load current and the on-resistance of the p-channe l mosfet. minimum required input voltage vselect under such conditions is the sum of the output voltage plus the voltage drop across the inductor and the p-channel mosfet switch. active output voltage discharge for smps the ISL80083 offers a feature to actively discharge the output voltage of smps via an internal bleeding resistor (typically 115 ? ) when the channel is disabled. this feature is enabled by default, but the output can be disabled through programming the control bit in smps_parameter register.
ISL80083 15 fn7886.1 may 15, 2013 3.0v clamp output the v3clamp is a 3v ldo sourced from vselect capable of providing up to 15ma. there is an internal clamp to prevent this output from exceeding 3.3v. 1v auxiliary output the 1v aux is an auxiliary output sourced from the 1v switcher. the 50m pfet is controlled by using i 2 c. there is approximately 5ms delay time from the enable to the output start-up. soft-start rise time is approximately 20s to prevent a switcher glitch. pulling osc_en low can also disable the 1vaux output. thermal shutdown when the die temperature of ISL80083 reaches +150c, the regulator is completely shut down and as the temperature drops to +120c (typical), the device resumes normal operation after initiate its soft-start cycle. figure 36. start-up and shutdown sequence 1v smps osc osc_en 1.8v ldo v3clamp reset 1vaux 1ms 1ms 1ms 1.5ms 1ms 1ms vselect 1v clk2p3out 1.8v 2.3v 3v 3.3v vin_host or vin_remote
ISL80083 16 fn7886.1 may 15, 2013 i 2 c compatible interface the ISL80083 offers an i 2 c compatible interface, using two pins: sclk for the serial clock and sdat for serial data respectively. according to the i 2 c specifications, there are internal 5k ? pull-up resistors for the clock and data signals connected to v3pclamp. signal timing specifications should satisfy the standard i 2 c bus specification. the maximum bit ra te is 400kb/s and more details regarding the i 2 c specifications can be found from philips. i 2 c slave address the ISL80083 serves as a slave device and the 7-bit default chip address is 1101100, as shown in figure 37. according to the i 2 c specifications, here the value of bit 0 determines the direction of the message (?0? means ?write? and ?1? means ?read?). i 2 c protocol figure 38 shows typical i 2 c-bus transaction protocols. figure 37. i 2 c slave address 1 r/w 1 0 1 1 0 0 bit 2 bit 3 bit 0 bit 1 bit 6 bit 7 bit 4 bit 5 msb lsb figure 38a. i 2 c write figure 38b. i 2 c read figure 38. s 0 a p slave address register address data byte 1 r/w a system host ISL80083h a ? acknowledge n ? not acknowledge s ? start p ? stop a s 0 a p slave address register address r/w p 1 slave address r/w n data byte n a a system host ISL80083h a ? acknowledge n ? not acknowledge s ? start p ? stop s
ISL80083 17 fn7886.1 may 15, 2013 i 2 c control registers all the registers are reset at initial start-up. control register parameters, address 0x00h ldo output voltage control register ldo_out, address 0x01h. table 2. real time osc adjustment register bit name access reset description b7 osc_trim r/w 0 reg00h value adjustment b6 osc_trim r/w 0 0111 1111 0111 1110 | | 0000 0001 0000 0000 1111 1111 | | 1000 0001 1000 0000 +127 +126 +1 0 -1 -2 -127 -128 b5 osc_trim r/w 0 b4 osc_trim r/w 0 b3 osc_trim r/w 0 b2 osc_trim r/w 0 b1 osc_trim r/w 0 b0 osc_trim r/w 0 table 3. ldo output voltage control registers bit name access reset description b7 1vaux_en r/w 1 1vaux enable selection. 0-enable, 1-disable b6 reserved r/w 1 b5 ldo_out-5 r/w 0 refer to table 4 for ldo output voltage settings b4 ldo_out-4 r/w 1 b3 ldo_out-3 r/w 0 b2 ldo_out-2 r/w 0 b1 ldo_out-1 r/w 1 b0 ldo_out-0 r/w 0 table 4. ldo output voltage settings ldoout <5:0> ldo output voltage (v) ldoout <5:0> ldo output voltage (v) ldoout <5:0> ldo output voltage (v) ldoout <5:0> ldo output voltage (v) 00h 0.9 10h 1.70 20h 2.50 30h 3.30 01h 0.95 11h 1.75 21h 2.55 31h 3.35 02h 1.00 12h 1.80 22h 2.60 32h 3.40 03h 1.05 13h 1.85 23h 2.65 33h 3.45 04h 1.1 14h 1.90 24h 2.70 34h 3.50 05h 1.15 15h 1.95 25h 2.75 35h 3.55 06h 1.20 16h 2.00 26h 2.80 36h 3.60 07h 1.25 17h 2.05 27h 2.85 08h 1.30 18h 2.10 28h 2.90 09h 1.35 19h 2.15 29h 2.95 0ah 1.40 1ah 2.20 2ah 3.00 0bh 1.45 1bh 2.25 2bh 3.05 0ch 1.50 1ch 2.30 2ch 3.10 0dh 1.55 1dh 2.35 2dh 3.15 0eh 1.60 1eh 2.40 2eh 3.20
ISL80083 18 fn7886.1 may 15, 2013 smps output voltage control register smps_out, address 0x02h caution: disable smps prior to changing from fixed output voltage to adjustable output volt age or from adju stable output voltage to fixed output voltage using i 2 c. table 5. buck converter output voltage control register bit name access reset description b7 osc_control r/w 1 33mhz oscillator control selection. 0-off, 1-on b6 smps_en r/w 1 smps enable selection. 0-disable, 1-enable b5 smps_pwm-5 r/w 0 refer to table 6 for smps output voltage setting b4 smps_pwm-4 r/w 0 b3 smps_pwm-3 r/w 1 b2 smps_pwm-2 r/w 1 b1 smps_pwm-1 r/w 1 b0 smps_pwm-0 r/w 1 table 6. smps output voltage setting smpsout <5:0> smps output voltage (v) smpsout <5:0> smps output voltage (v) smpsout <5:0> smps output voltage (v) 00h 0.625 1dh 1.375 3bh 2.125 01h 0.650 1eh 1.400 3ch 2.150 02h 0.675 1fh 1.425 3dh 2.175 03h 0.700 20h 1.450 3eh 2.200 04h 0.725 21h 1.475 3fh 2.225 05h 0.750 22h 1.500 06h 0.775 23h 1.525 07h 0.800 24h 1.550 08h 0.825 25h 1.575 09h 0.850 26h 1.600 0ah 0.875 27h 1.625 0bh 0.900 28h 1.650 0ch 0.925 29h 1.675 0dh 0.950 2ah 1.700 0eh 0.975 2bh 1.725 0fh 1.000 2ch 1.750 10h 1.025 2dh 1.775 11h 1.050 2eh 1.800 12h 1.075 2fh 1.825 13h 1.100 30h 1.850 14h 1.125 31h 1.875 15h 1.150 32h 1.900 16h 1.175 33h 1.925 17h 1.200 34h 1.950 18h 1.225 35h 1.975 19h 1.250 36h 2.000 19h 1.275 37h 2.025 1ah 1.300 38h 2.050 1bh 1.325 39h 2.075 1ch 1.350 3ah 2.100
ISL80083 19 fn7886.1 may 15, 2013 smps output voltage control register smps_sleep, address 0x03h caution: disable smps prior to changing from fixed output voltage to adjustable output volt age or from adju stable output voltage to fixed output voltage using i 2 c. table 7. buck converter output voltage control register bit name access reset description b7 reset _dy r/w 0 reset delay time, 00 to 1.07ms 01 to 8.4ms b6 smpssr r/w 0 smps slew rate setting, 0 to 0.19mv/s 1 to 0.38mv/s b5 smps_pfm-5 r/w 0 refer to table 8 for smps output voltage setting. b4 smps_pfm-4 r/w 0 b3 smps_pfm-3 r/w 1 b2 smps_pfm-2 r/w 1 b1 smps_pfm-1 r/w 1 b0 smps_pfm-0 r/w 1 table 8. smps output voltage setting smpsout <5:0> smps output voltage (v) smpsout <5:0> smps output voltage (v) smpsout <5:0> smps output voltage (v) 00h 0.625 1ch 1.350 39h 2.075 01h 0.650 1dh 1.375 3ah 2.100 02h 0.675 1eh 1.400 3bh 2.125 03h 0.700 1fh 1.425 3ch 2.150 04h 0.725 20h 1.450 3dh 2.175 05h 0.750 21h 1.475 3eh 2.200 06h 0.775 22h 1.500 3fh 2.225 07h 0.800 23h 1.525 08h 0.825 24h 1.550 09h 0.850 25h 1.575 0ah 0.875 26h 1.600 0bh 0.900 27h 1.625 0ch 0.925 28h 1.650 0dh 0.950 29h 1.675 0eh 0.975 2ah 1.700 0fh 1.000 2bh 1.725 10h 1.025 2ch 1.750 11h 1.050 2dh 1.775 12h 1.075 2eh 1.800 13h 1.100 2fh 1.825 14h 1.125 30h 1.850 15h 1.150 31h 1.875 16h 1.175 32h 1.900 17h 1.200 33h 1.925 18h 1.225 34h 1.950 19h 1.250 35h 1.975 19h 1.275 36h 2.000 1ah 1.300 37h 2.025 1bh 1.325 38h 2.050
ISL80083 20 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7886.1 may 15, 2013 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change may 15, 2013 fn7886.1 initial release
ISL80083 21 fn7886.1 may 15, 2013 package outline drawing w5x5.25b 5x5 array 25 ball with 0.40 pitch wafe r level chip scale package (wlcsp) rev 2, 12/11 bottom view side view typical recommended land pattern top view nsmd refers to non-solder mask defined pad design per dimension and tolerance per asmey 14.5m-1994, 3. 2. all dimensions are in millimeters. 1. notes: and jesd 95-1 spp-010. intersil tech brief tb451 located at: nsmd package 0.10 (4x) x y z 0.05 z seating plane 3 pin 1 (a1 corner) 0.250.03 0.190.03 0.55 m ax 0.3050.025 2.110.03 2.130.03 1.60 1.60 0.40 a b 5 4 3 c d 12 e 0.40 25x 0.2250.03 0.25 0.225 0.40 0.10 z x y 0.05 z outline http://www.intersil.com/data/tb/tb451.pdf . 0.265 0.254

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